EDA七段译码器实验报告
实验目的
掌握七段译码器
实验设备
quartus II 5.0
实验内容
library ieee;
use ieee.std_logic_1164.all;
entity qdymq is
port(a:in std_logic_vector(3 downto 0);
led:out std_logic_vector(7 downto 0));
end qdymq;
architecture one of qdymq is
begin
with a select
led<="00111111"when"0000", "00000110"when"0001", "01011011"when"0010", "01001111"when"0011", "01100110"when"0100", "01101101"when"0101", "01111101"when"0110", "00000111"when"0111", "01111111"when"1000", "01101111"when"1001", "ZZZZZZZZ"when others; end one;
1 总结 七段译码器原理图功能正确。
